1. Field of the Invention
The present invention generally relates to a non-volatile semiconductor memory device. More particularly, the present invention relates to the memory array structure of a flash memory.
2. Description of the Background Art
Recently, a flash memory capable of non-volatile data storage (batch-erasable, electrically rewritable read only memory) goes mainstream. In particular, a MONOS (Metal Oxide Nitride Oxide Silicon) memory transistor cell has attracted attention in such a flash memory because of its low costs, small area, and charge storage portion. The MONOS memory transistor cell is characterized in that a nitride film is used as the charge storage portion instead of a floating gate used in the conventional examples.
The MONOS memory transistor cell is different from the floating gate: structure in that the polycrystalline silicon of floating gate is replaced with a nitride film.
FIGS. 10A, 10B and 10C illustrate normal write, read and erase operations of the MONOS memory transistor cell, respectively.
Referring to FIGS. 10A, 10B and 10C, MONOS memory transistor cell MC is formed from a stacked layer of three insulating films (i.e., an oxide film;4, a nitride film 5, and an oxide film 6) and a polycrystalline silicon of control gate 7 on a P-type semiconductor substrate 1. Near the stacked gate on P-type semiconductor substrate 1, N-channel diffusion regions 2, 3 are formed in a self-aligned manner. Memory transistor cell MC thus corresponds to an N-channel field effect transistor formed on P-type semiconductor substrate 1.
FIG. 10A illustrates normal write operation of MONOS memory transistor cell MC.
When 0 V is applied to P-type semiconductor substrate 1, 10 V is applied to control gate 7, 5 V is applied to diffusion region 2, and 0 V is applied to diffusion region 3, channel electrons are accelerated by a steep electric field created in diffusion region 2 of the memory transistor cell. Those accelerated electrons which overcome the barrier height of the oxide film are trapped on the side of diffusion region 2 in nitride film 5 (bit 1). As a result, the threshold voltage of memory transistor cell MC is increased to render memory transistor cell MC in the written state storing data xe2x80x9c0xe2x80x9d. For example, the data of bit 1 is xe2x80x9c0xe2x80x9d in the written state caused by the trapped electrons, and xe2x80x9c1xe2x80x9d in the state where no data is written (i.e., in the erased state). The following description is given on the assumption that the data is xe2x80x9c0xe2x80x9d in the written state and xe2x80x9c1xe2x80x9d in the erased state.
When the applied voltages to diffusion regions 2, 3 are reversed, i.e., when 0 V is applied to diffusion region 2 and 5 V is applied to diffusion region 3 as shown in parentheses in FIG. 10A, the electrons are trapped on the side of diffusion region 3 in nitride film 5 (bit 2). As a result, the threshold voltage of memory transistor cell MC is increased to render memory transistor cell MC in the written state storing data xe2x80x9c0xe2x80x9d. Accordingly, the data of bit 2 is xe2x80x9c0xe2x80x9d in the written state caused by the trapped electrons, and xe2x80x9c1xe2x80x9d in the erased state.
This MONOS structure traps electrons in non-covalent bonds (dangling bonds) that are distributed in nitride film 5 at random. Electrons are stored at different positions in nitride film 5 (i.e., on the sides of diffusion regions 2 and 3 in nitride film 5) one bit each, enabling two-bit/cell data storage.
FIG. 10B illustrates read operation of MONOS memory transistor cell MC.
First, operation of reading bit 1 on the side of diffusion region 2 in nitride film 5 will be described.
A voltage of 0 V is applied to P-type semiconductor substrate 1, 3 V is applied to control gate 7, 0 V is applied to diffusion region 2, and 2 V is applied to diffusion region 3. It is herein assumed that memory transistor cell MC is in the written state on the side of diffusion region 2 in nitride film 5, that is, electrons have been trapped in nitride film 5. In this case, a high threshold voltage inhibits memory transistor cell MC from being turned ON, and no current path is formed from diffusion region 3 to diffusion region 2. As a result, xe2x80x9c0xe2x80x9d can be read as the data of bit 1. On the other hand, when memory transistor cell MC is in the erased state on the side of diffusion region 2 in nitride film 5, a low threshold voltage allows memory transistor cell MC to be turned ON, and a current path is formed from diffusion region 3 to diffusion region 2. As a result, xe2x80x9c1xe2x80x9d can be read as the data of bit 1.
Hereinafter, operation of reading the data of bit 2 on the side of diffusion region 3 in nitride film 5 will be described.
The applied voltages to diffusion regions 2, 3 are reversed. More specifically, 0 V is applied to P-type semiconductor substrate 1, 3 V is applied to control gate 7, 2 V is applied to diffusion region 2, and 0 V is applied to diffusion region 3, as shown in parentheses in FIG. 10B. It is herein assumed that memory transistor cell MC is in the written state on the side of diffusion region 3 in nitride film 5, that is, electrons have been trapped in nitride film 5. In this case, a high threshold voltage inhibits memory transistor cell MC from being turned ON, and no current path is formed from diffusion region 2 to diffusion region 3. As a result, xe2x80x9c0xe2x80x9d can be read as the data of bit 2. On the other hand, when memory transistor cell MC is in the erased state on the side of diffusion region 3 in nitride film 5, a low threshold voltage allows memory transistor MC to be turned ON, and a current path is formed from diffusion region 2 to diffusion region 3. As a result, xe2x80x9c1xe2x80x9d can be read as the data of bit 2.
Accordingly, by adjusting the applied voltages to diffusion regions 2, 3, bit 1 and bit 2 can be read according to whether a current path is formed or not. This enables two-bit/cell read operation.
FIG. 10C illustrates erase operation of MONOS memory transistor cell MC.
First, operation of erasing bit 1 on the side of diffusion region 2 in nitride film 5 will be described.
It is herein assumed that 0 V is applied to P-type semiconductor substrate 1 and control gate 7, 10 V is applied to diffusion region 2, and diffusion region 3 is in the open state (OPEN).
In this case, it flows a Fowler-Nordheim current from bit 1 on the side of diffusion region 2 trapped the electrons in nitride film 5 to substrate region 1 or diffusion region 2. The electrons are thus removed from the side of diffusion region 2 in nitride film 5. In this state, memory transistor cell MC has a reduced threshold voltage.
Hereinafter, operation of erasing bit 2 on the side of diffusion region 3 in nitride film 5 will be described.
It is herein assumed that 0 V is applied to P-type semiconductor substrate 1 and control gate 7, 10 V is applied to diffusion region 3, and diffusion region 2 is in the open state, as shown in parentheses in FIG. 10C.
In this case, it flows a Fowler-Nordheim current from bit 2 on the side of diffusion region 3 trapped the electrons in nitride film 5 to substrate region 1 or diffusion region 3. The electrons are thus removed from the side of diffusion region 3 in nitride film 5. In this state, memory transistor cell MC has a reduced threshold voltage.
Note that, when 10 V is applied to both diffusion regions 2, 3, electrons are removed from both bits 1, 2. The data is erased in this way.
FIG. 11 shows the structure of an array of a flash memory using the above MONOS memory transistor cells MC (hereinafter, referred to as NROM(R) memory array).
Referring to FIG. 11, the NROM(R) memory array includes identical memory block units MBU arranged in a matrix. Adjacent two memory block units MBU are electrically coupled to each other.
Memory block unit MBU1 located in the center will now be described. Since the other memory block units MBU have the same circuit structure as that of memory block unit MBU1, detailed description thereof will not be repeated.
Memory block unit MBU1 includes memory transistor cells MC(0.0) to MC(31.3) arranged in a matrix. Memory transistor cell MC(i.j) herein indicates a memory transistor cell located at the intersection of the ith row and the jth column (where i, j is an integer equal to or larger than zero).
Memory block unit MBU1 further includes word lines WL0 to WL31 (hereinafter, generally referred to as word lines WL), diffusion bit lines BL0 to BL3 (hereinafter, generally referred to as diffusion bit lines BL), main bit lines MBL0, MBL1 (hereinafter, generally referred to as main bit lines MBL), and gate units gtu1, gtu2. Word lines WL0 to WL31 correspond to the rows of memory transistor cells MC(0.0) to MC(31.3), respectively. Diffusion bit lines BL0 to BL3 correspond to the columns of memory transistor cells MC(0.0) to MC(31.3), respectively. Gate unit gtu1 electrically couples diffusion bit lines BL0, BL2 to main bit line MBL0. Gate unit gtu2 electrically couples diffusion bit lines BL1, BL3 to main bit line MBL1.
Gate unit gtu1 includes a gate transistor gt1 for electrically coupling diffusion bit line BL0 to main bit line MBL0, and a gate transistor gt2 for electrically coupling diffusion bit line BL2 to main bit line MBL0. Gate transistors gt1, gt2 are activated by gate select lines gs1, gs2, respectively.
Gate unit gtu2 includes a gate transistor gt3 for electrically coupling diffusion bit line BL1 to main bit line MBL1, and a gate transistor gt4 for electrically coupling diffusion bit line BL3 to main bit line MBL1. Gate transistors gt3, gt4 are activated by gate select lines gs3, gs4, respectively.
A plurality of non-volatile memory transistor cells MC arranged in the same column are herein collectively referred to as a column memory unit MU. For example, memory transistor cells MC(0.0) to MC(31.0) forms a column memory unit MU.
Each column memory unit MU is arranged between adjacent two of diffusion bit lines BL0 to BL4. Adjacent two column memory units MU share diffusion bit line BL located therebetween. Column memory unit MU of memory transistor cells MC(0.0) to MC (31.0) shares diffusion bit line BL0 with column memory unit MC in the left memory block unit MBU.
Memory block unit MBU2 includes memory transistor cells MC(0.4) to MC(31.7) arranged in a matrix, gate units gtu3, gtu4, diffusion bit lines BL4 to BL7, and main bit lines MBL2, MBL3. Gate unit gtu3 includes gate transistors gt5, gt6. Gate unit gtu4 includes gate transistors gt7, gt8. Since the connection between the above elements is the same as that in memory block unit MBU1, detailed description thereof will not be repeated. Column memory unit MU of memory transistor cells MC(0.7) to MC(31.7) is electrically coupled to diffusion bit line BL included in the right memory block unit MBU. Note that memory block unit MBU generally refers to memory block units MBU1, MBU2 and the like.
The above NROM(R) memory array structure allows two-bit/cell read operation by using small MONOS memory transistor cells, shares a bit line between adjacent two column memory units MU, and uses a diffusion layer for the bit lines. This enables improvement in integration.
Hereinafter, operation of simultaneously reading bit 1 on the side of diffusion region 2 of memory transistor cell MC(0.1) of memory block unit MBU1 (hereinafter, generally referred to as right bit) and the right bit of memory transistor cell MC(0.5) of memory block unit MBU2 will be considered.
FIG. 12 is a fining chart of the operation of simultaneously reading the respective right bits of memory transistor cells MC(0.1), MC(0.5).
Referring to FIG. 12, in the operation of reading the right bits, main bit lines MBL1, MBL3 first rise to 2 V. The other main bit lines MBL0, MBL2 are at 0 V. Gate select lines gs2, gs3 then rise to 8 V (xe2x80x9cHxe2x80x9d level). In response to this, gate transistors gt3, gt7 are turned ON, and the voltage (2 V) on main bit lines MBL1, MBL3 is transmitted to diffusion bit lines BL1, BL5. Gate transistors gt2, gt6 are also turned ON, and diffusion bit lines BL2, BL6 are electrically coupled to main bit lines MBL0, MBL2, respectively. The other word lines WLs other than word line WL0 are at 0 V. In the operation of reading the right bits, gate select lines gs1, gs4 are at 0 V.
At time t1, word line WL0 is activated and rises to 3 V. The right bits of memory transistor cells MC(0.1), MC(0.5) are read in this way.
It is herein assumed that the right bits of memory transistor cells MC(0.1), MC(0.5) are in the erased state. In this case, the right-bit read operation is performed as follows:
Memory transistor cells MC(0.1), MC(0.5) are turned ON in response to the voltage from word line WL0, because of their low threshold voltage. This raises the voltage levels of diffusion bit lines BL2, BL6 and thus the voltages of main bit lines MBL0, MBL2 electrically connected thereto, respectively. Once the voltages rise to such a level that allows a not-shown sense amplifier connected to main bit lines MBL0, MBL2 to read the data, that is, at time t2, the voltages on main bit lines MBL1, MBL3 are caused to fall.
The voltages of diffusion bit lines BL1, BL5 fall responsively. At time t3 the voltages of main bit lines MBL1, MBL3 and diffusion bit lines BL1, BL5 fall to 0 V, the voltages of gate select lines gs2, gs3 and word line WL0 are caused to fall.
It is herein assumed that the right bits of memory transistor cells MC(0.1), MC(0.5) have already been in the written state. In this case, the right-bit read operation is performed as follows:
Memory transistor cells MC(0.1), MC(0.5) will not be turned ON in response to the rise of word line WL0 at time t1, because of their high threshold voltage.
However, if MC(0.2) to MC(0.4) of memory transistor cells MC(0.1) to MC(O.5) are in the erased state, all memory transistor cells MC(0.2) to MC(0.4) are turned ON because of their low threshold voltage.
The voltages of diffusion bit lines BL5, BL2 are 2V and 0 V, respectively. Adjacent diffusion bit lines BL are electrically connected to each other through corresponding memory transistor cells MC. Therefore, a current path is formed from diffusion bit line BL5 to diffusion bit line BL2 in response to the rise of word line WL0. In other words, a through current path is formed. Provided that the right bit of memory transistor cell MC(0.1) is in the written state, a through current path is formed from diffusion bit line BL5 to diffusion bit line BL2 even if memory transistor cell MC(0.1) is not turned ON. This raises the voltage levels of diffusion bit line BL2 and main bit line MBL0. As a result, the sense amplifier connected to main bit line MBL0 may erroneously recognize the written state of the right bit of memory transistor cell MC(0.1) as the erased state.
In the operation of simultaneously writing data to memory transistor cells MC(0.1), MC(0.5), a similar through current path may possibly be formed. Such a through current path may cause the data to be erroneously written to an unintended memory transistor cell MC.
It is an object of the present invention to provide a non-volatile semiconductor memory device having a memory array structure that prevents generation of a through current path.
A non-volatile semiconductor memory device according to the present invention includes a memory array including a plurality of non-volatile memory transistor cells arranged in a matrix. The plurality of non-volatile memory transistor cells each has a threshold voltage according to a storage data level. The memory array is divided into a plurality of memory blocks. Each of the plurality of memory blocks includes a plurality of memory cell columns, and a plurality of bit lines arranged along column direction on both sides of each corresponding memory cell column, respectively. Each of the bit lines is arranged between adjacent two memory cell columns being shared by the adjacent two memory cell columns. The memory array includes a plurality of isolating portions each provided between adjacent two memory blocks, for electrically isolating two memory blocks from each other.
Preferably, a read operation and a write operation are performed one bit per memory block.
Accordingly, a main advantage of the present invention is as follows: each isolating portion provided between adjacent memory blocks electrically isolates the corresponding memory blocks from each other. Therefore, when write operation and read operation are performed one bit per memory block, no through current path (current path between memory blocks) is formed. As a result, erroneous write and read operation can be prevented.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.